1. Field of the Invention
The present invention relates to multi-port semiconductor memory devices, and more particularly, to a multi-port semiconductor memory device and a signal input/output method thereof, in which different signal input/output ports are used depending on whether the device is being operated in a normal mode or a test mode.
2. Description of the Related Art
Most semiconductor memory devices, including RAM (Random Access Memory), have one input/output port having a plurality of input/output pin sets to communicate with an external processor.
FIG. 1 is a block diagram of a semiconductor memory device illustrating access paths according to conventional art, and in particular illustrates access paths in a conventional semiconductor memory device having four memory banks and a single input/output port.
As shown in FIG. 1, a conventional semiconductor memory device includes a memory array 10 having four memory banks 10a, 10b, 10c, and 10d, and a single input/output port 20. The input/output port 20 may be provided as an input/output path of command signals, address signals, data signals, and other signals, etc. between a semiconductor memory device and an external processor.
All of memory banks 10a, 10b, 10c, and 10d constituting the memory array 10 are configured to be accessed through the one input/output port 20. In FIG. 1, the arrows indicate access paths.
Such conventional semiconductor memory devices having one port have problems in terms of access speed or access efficiency. For example, in FIG. 1, in a case where first data is stored in A bank 10a in a first operation, and second data is read out from B bank 10b in a second operation different from the first operation, the operations must be performed at separate time intervals. That is, the first operation is performed and then the second operation is performed, or vice-versa, which requires an at least one additional time interval and precludes possible higher speed and higher efficiency operations.
In order to solve the problems, a multi-port semiconductor memory device was provided in U.S. Pat. No. 5,815,456 issued on Sep. 29, 1998 as an example of conventional multi-port semiconductor memory device, in which the communication was performed through a plurality of processors. Thus, in this multi-port semiconductor memory device, memory cells may be accessed through a plurality of input/output ports.
However, in this and other conventional respective multi-port semiconductor memory devices, access paths between input/output ports and memory regions, e.g., memory banks, are predetermined in hardware, thus making it difficult to vary the configuration thereof, such as varying configurations between a operation mode and a test mode to test the semiconductor memory device. In particular, when test pins of a test equipment are not present to test the semiconductor memory device, the test cannot be performed. Furthermore, even if the test pins are present, the access paths are predetermined, thus requiring a test to be separately performed through predetermined input/output ports, which may decrease the test efficiency.